具有預載Preload 與 計數致能count enable的 2進制Binary計數器

具有預載Preload 與 計數致能count enable的 2進制Binary計數器

輸入 ： DIP SW  Data[7..0]
              預載Preload
                 clk ---clock
,up_down ---up / down counter
,ena                ---enable counter
,load : in std_logic; --load 8-bit Data in 
data_in : in std_logic_vector(7 downto 0); --Data in
輸出       d0,d1七段顯示器 靜態方式  共陰極
           : out std_logic_vector(6 downto 0) ---7-segment digit0 digit1

------------------------------------------
--with Preload & Enable 8 bit Counter
--input : Clock 48Mhz divide into 1Hz
--output : 2 digits 7-segment
------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
------------------------------------------
entity Preload_CNT is
port(
clk ---clock
,up_down ---up / down counter
,ena ---enable counter
,load : in std_logic; --load 8-bit Data in 
data_in : in std_logic_vector(7 downto 0); --Data in
d0,d1 : out std_logic_vector(6 downto 0) ---7-segment digit0 digit1
);
end Preload_CNT;
------------------------------------------
architecture arch_count of Preload_CNT is 

signal s0,s1: std_logic_vector (6 downto 0);
signal cnt : std_logic_vector(7 downto 0);
signal freq1: integer range 0 to 23999999 := 0;
signal hz1 : std_logic := '0'; 

----------------------------------------------
component seg_d7 is
port(
     bin : in std_logic_vector(3 downto 0);
     seg7: out std_logic_vector(6 downto 0)
     );
end component;

------------------------------------------
begin
------------------------------------------
Clk_generator: 
process (clk)
  begin 
    if(clk'event and clk = '1') then
if(freq1 >= 23999999) then 
                freq1 <= 0;
                hz1 <= not hz1;
        else
                freq1 <= freq1 + 1;
        end if;
    end if;
end process ;
------------------------------------------    
Count_process: 
process (hz1)
variable dir : integer ;
begin
if (up_down='1') then
dir:=1 ; ----up counter
else
dir:=-1 ; ----down counter
end if;
    --------------------------
    if(hz1'event and hz1 = '1') then 
   if (load='1') then  -----load data
cnt <= data_in ;
  elsif  (ena='1') then  -----enable counter active
cnt <= cnt + dir ; ---up / down counter dir=1 /-1
        end if;
    end if;
    
 end process;      

------------------------------------------   
    u1:seg_d7 port map(cnt(7 downto 4),d1);

    u0:seg_d7 port map(cnt(3 downto 0),d0);
------------------------------------------       

end arch_count;

----------------------------------------------------------------

---------------------------------------------

--Binary to 7segment

--7segment--> Common cathodee 7-segment display

----a,b,c,d,e,f,g---

---------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

USE ieee.std_logic_unsigned.all;

ENTITY seg_d7 IS

PORT(

bin : in std_logic_vector(3 downto 0);

seg7 : out std_logic_vector(6 downto 0)

);

END seg_d7;

ARCHITECTURE arch_seg_d7  OF seg_d7 IS

BEGIN --a,b,c,d,e,f,g---

seg7 <= "1111110" when bin="0000" else

"0110000" when bin="0001" else

"1101101" when bin="0010" else

"1111001" when bin="0011" else

"0110011" when bin="0100" else

"1011011" when bin="0101" else

"1011111" when bin="0110" else

"1110000" when bin="0111" else

"1111111" when bin="1000" else

"1111011" when bin="1001" else

"1110111" when bin="1010" else

"0011111" when bin="1011" else

"1001110" when bin="1100" else

"0111101" when bin="1101" else

"1001111" when bin="1110" else

"1000111" when bin="1111" else

"0000000";

--seg7 <= "0000001" when bin="0000" else

-- "1001111" when bin="0001" else

-- "0010010" when bin="0010" else

-- "0000110" when bin="0011" else

-- "1001100" when bin="0100" else

-- "0100100" when bin="0101" else

-- "0100000" when bin="0110" else

-- "0001111" when bin="0111" else

-- "0000000" when bin="1000" else

-- "0000100" when bin="1001" else

-- "0001000" when bin="1010" else

-- "1100000" when bin="1011" else

-- "0110001" when bin="1100" else

-- "1000010" when bin="1101" else

-- "0110000" when bin="1110" else

-- "0111000" when bin="1111" else

-- "1111111";

END arch_seg_d7 ;

----------------------------------------------------------------

To	Direction	Location	I/O Bank
clk	Input	PIN_21	1
d0[6]	Output	PIN_37	4
d0[5]	Output	PIN_39	4
d0[4]	Output	PIN_41	4
d0[3]	Output	PIN_43	4
d0[2]	Output	PIN_45	4
d0[1]	Output	PIN_49	4
d0[0]	Output	PIN_51	4
d1[6]	Output	PIN_57	4
d1[5]	Output	PIN_59	4
d1[4]	Output	PIN_61	4
d1[3]	Output	PIN_63	4
d1[2]	Output	PIN_67	4
d1[1]	Output	PIN_69	4
d1[0]	Output	PIN_71	4
data_in[7]	Input	PIN_15	1
data_in[6]	Input	PIN_13	1
data_in[5]	Input	PIN_11	1
data_in[4]	Input	PIN_7	1
data_in[3]	Input	PIN_5	1
data_in[2]	Input	PIN_3	1
data_in[1]	Input	PIN_1	1
data_in[0]	Input	PIN_143	2
ena	Input	PIN_31	1
load	Input	PIN_29	1
up_down	Input	PIN_32	1