因為SW I/O不夠 故利用SW[16] ,SW[17] 來分別載入被加數及加數
SW[17]=1 載入被加數
SW[16]=1 載入加數
module _4digit_BCD_Adder(SW, LEDR, LEDG , CLOCK_27 ,KEY ,HEX0 ,HEX1 ,HEX2,HEX3,,HEX4,HEX5,HEX6,HEX7 );
input [17:0] SW; // toggle switches
input [7:0] KEY; // Push bottom
input CLOCK_27; //Clock 27MHz , 50Mhz
output [17:0] LEDR; // red LEDS
output [8:0] LEDG; // green LEDs
output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7; //7-segment display
reg [3:0] A3,A2,A1,A0;
reg [3:0] B3,B2,B1,B0;
wire [3:0] S3,S2,S1,S0;
wire C3,C2,C1,C0;
wire A_load,B_load; //A3,A2,A1,A0 load to temp_reg_A;
//B3,B2,B1,B0 load to temp_reg_B;
wire [7:0] segout0; //HEX 0
wire [7:0] segout1; //HEX 1
wire [7:0] segout2; //HEX 2
wire [7:0] segout3; //HEX 3
wire [7:0] segout4; //HEX 4
assign A_load=SW[17];
assign B_load=SW[16];
assign LEDR[17:16]=SW[17:16];
always@( A_load or B_load)
begin
if (A_load==1'b1)
begin
A3=SW[15:12];
A2=SW[11:8];
A1=SW[7:4];
A0=SW[3:0];
end
if (B_load==1'b1)
begin
B3=SW[15:12];
B2=SW[11:8];
B1=SW[7:4];
B0=SW[3:0];
end
end
_4bit_BCD_Adder U0(.A(A0),.B(B0),.Cin(1'b0),.S(S0),.Cout(C0));
_4bit_BCD_Adder U1(.A(A1),.B(B1),.Cin(C0),.S(S1),.Cout(C1));
_4bit_BCD_Adder U2(.A(A2),.B(B2),.Cin(C1),.S(S2),.Cout(C2));
_4bit_BCD_Adder U3(.A(A3),.B(B3),.Cin(C2),.S(S3),.Cout(C3));
//Display BCD Sum to 7-segment Display
_7seg UUT0(.hex(S0),.seg(segout0));
_7seg UUT1(.hex(S1),.seg(segout1));
_7seg UUT2(.hex(S2),.seg(segout2));
_7seg UUT3(.hex(S3),.seg(segout3));
_7seg UUT4(.hex({3'b0,C3}),.seg(segout4));
assign HEX0=segout0[6:0];
assign HEX1=segout1[6:0];
assign HEX2=segout2[6:0];
assign HEX3=segout3[6:0];
assign HEX4=segout4[6:0];
assign HEX5=7'h7f; //Blank 7-segment
assign HEX6=7'h7f;
assign HEX7=7'h7f; //set 1 => off LED
endmodule
//------------------------------------
//4-bit BCD adder
//Filename : BCDadder4.v
//------------------------------------
module _4bit_BCD_Adder(A,B,Cin,S,Cout);
//(S, Cout, Cin, A, B);
output [3:0] S; //Sumation output
output Cout; //Carry out
input Cin; //Carry in
input [3:0] A, B; //Input data
reg [3:0] A_tmp,B_tmp;
wire [3:0] S_tmp;
wire C4;
reg [3:0] B_mod;
reg F;
always @ ( A or B )
begin
if (A<10)
A_tmp = A; //若是>9 則為9
else
A_tmp =4'b1001;
if (B<10)
B_tmp = B; //若是>9 則為9
else
B_tmp =4'b1001;
end
//4-bit binary adder
adder4 BINADD(
.S(S_tmp),
.Cout(C4),
.Cin(Cin),
.A(A_tmp),
.B(B_tmp)
);
//Modify binary code with '0110'
adder4 MODADD(
.S(S), //Call By Name
.Cout(),
.Cin(1'b0),
.A(S_tmp),
.B(B_mod)
);
always @ (Cin or A or B or C4 or S_tmp)
begin
//F=C4+S3(S2+S1)
F = (C4 | (S_tmp[3] & (S_tmp[2] | S_tmp[1])));
B_mod = {1'b0, F, F, 1'b0}; //Modified code
end
assign Cout = F;
endmodule
//----------------------
//4-bit unsigned adder
//Filename : adder4.v
//----------------------
module adder4(S, Cout, A, B, Cin);
output [3:0] S; //4-bit sum
output Cout; //Carry out
input [3:0] A, B; //Inputs
input Cin; //Carry in
//Assign the sum of (A+B+Cin) to Cout and Sum
assign {Cout, S} = A + B + Cin;
endmodule
//-----------------------------------------
//Common-cathod seven segment display
//using case.....endcase statement
//Filename : sevenseg_case.v
//-----------------------------------------
module _7seg(hex , seg);
input [3:0] hex;
output [7:0] seg;
reg [7:0] seg;
// segment encoding
// 0
// ---
// 5 | | 1
// --- <- 6
// 4 | | 2
// ---
// 3
always @(hex)
begin
case (hex)
// Dot point is always disable
4'b0001 : seg = 8'b11111001; //1 = F9H
4'b0010 : seg = 8'b10100100; //2 = A4H
4'b0011 : seg = 8'b10110000; //3 = B0H
4'b0100 : seg = 8'b10011001; //4 = 99H
4'b0101 : seg = 8'b10010010; //5 = 92H
4'b0110 : seg = 8'b10000010; //6 = 82H
4'b0111 : seg = 8'b11111000; //7 = F8H
4'b1000 : seg = 8'b10000000; //8 = 80H
4'b1001 : seg = 8'b10010000; //9 = 90H
4'b1010 : seg = 8'b10001000; //A = 88H
4'b1011 : seg = 8'b10000011; //b = 83H
4'b1100 : seg = 8'b11000110; //C = C6H
4'b1101 : seg = 8'b10100001; //d = A1H
4'b1110 : seg = 8'b10000110; //E = 86H
4'b1111 : seg = 8'b10001110; //F = 8EH
default : seg = 8'b11000000; //0 = C0H
endcase
end
endmodule
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