Design of Serial In - Serial Out Shift Register using d_flip flop.v Parallel IN - Serial OUT Shift Register.v

// File        : Design of Serial In - Serial Out Shift Register using d_flip flop.v

module siso ( din ,clk ,reset ,dout );

output dout ;

input din ;
input clk ;
input reset ;  
wire [2:0]s;

d_flip_flop u0 (.din(din),
.clk(clk),
.reset(reset),
.dout(s[0]));


d_flip_flop u1 (.din(s[0]),
.clk(clk),
.reset(reset),
.dout(s[1]));


d_flip_flop u2 (.din(s[1]),
.clk(clk),
.reset(reset),
.dout(s[2]));


d_flip_flop u3 (.din(s[2]),
.clk(clk),
.reset(reset),
.dout(dout));


endmodule




// -------------- D flip flop  design - -----------------------



//-----------------------------------------------------------------------------
//
// Title       : d_flip_flop
// Design      : upload_design1
// Author      : Naresh Singh Dobal
// Company     : nsd
//
//-----------------------------------------------------------------------------
//
// File        : d_flip_flop.v



module d_flip_flop ( din ,clk ,reset ,dout );

output dout ;
reg dout;

input din ;
input clk ;
input reset ;

always @ (posedge clk)
begin
if (reset)
dout <= 1;
else
dout <= din;
end

endmodule






// File        : Parallel IN -  Serial OUT Shift Register.v


module parallel_in_serial_out ( din ,clk ,reset ,load ,dout );

output dout ;
reg dout ;

input [3:0] din ;
wire [3:0] din ;
input clk ;
wire clk ;
input reset ;
wire reset ;
input load ;
wire load ;

reg [3:0]temp;

always @ (posedge (clk)) begin
if (reset)
temp <= 1;
else if (load)
temp <= din;
else begin
dout <= temp[3];
temp <= {temp[2:0],1'b0};
end
end

endmodule